Single Event Effects Explained: SEU, MBU, SEFI, SET, SEL, SEB and SEGR

A single event effect is what happens when one ionizing particle deposits enough charge in a small enough volume of a semiconductor to change its state or trigger a failure. The particle is a heavy ion from the galactic cosmic ray background, a heavy ion from a solar particle event, or a proton that produces a heavy recoil in a nuclear reaction inside the device. The effects fall into a handful of named categories, and the names matter because each carries a different consequence and a different remedy.

1. Two words first: LET and cross section

Linear energy transfer (LET) is how much energy a particle deposits per unit path length, quoted in MeV cm2/mg so that it is independent of material density. Low LET particles (protons, at a fraction of one) deposit little; the heaviest cosmic ray ions reach LET around 100. A part's threshold LET is the lowest LET at which an effect is observed; a threshold above about 75 MeV cm2/mg means the effect is practically unreachable in space, which is why 75 appears in so many requirements.

Cross section is the effective area a device presents to the effect: the number of events divided by the fluence of particles per square centimetre that produced them. It rises from zero at the threshold LET to a saturated value at high LET, and the rising curve is almost always described by a four parameter Weibull. Cross section times the flux of particles above the relevant LET gives the rate. The cross section tool fits the curve and the rate tool integrates it against an environment.

2. Non destructive effects

Single event upset (SEU)

A bit flips. The charge from one particle track is collected by a storage node in a memory cell, latch or flip flop and is enough to change the stored state. The device is undamaged; rewriting the bit restores it. SEU is the most common effect, present in essentially every SRAM, DRAM, register file and flip flop, with per bit cross sections that shrink with feature size while the number of bits grows. The consequence depends entirely on what the bit was doing: a pixel in a buffer is nothing, an instruction in program memory is a crash, a bit in a command register can fire a thruster. Mitigation is error detection and correction with scrubbing, redundancy and voting, and periodic refresh; the EDAC tool computes what survives.

Multiple bit upset (MBU) and multiple cell upset (MCU)

One particle upsets more than one cell. In modern memories a single track can flip several adjacent cells, and if two of them belong to the same protected word the single error correcting code cannot fix it. This is why memory designers interleave the bits of a word physically, and why the interleave distance is one of the most important undocumented numbers in a memory datasheet. The fraction of events that are multi cell rises from a few percent at old nodes to more than half at advanced ones.

Single event functional interrupt (SEFI)

The device stops working normally until it is reset or power cycled. The upset landed in a control register, a state machine, a phase locked loop or a configuration bit rather than in a data cell. SEFIs are characteristic of complex devices: processors, FPGAs, DRAM and flash controllers, converters with internal calibration. The device is not damaged, but the function it performed is gone for the duration of the recovery, and the recovery may need a power cycle the system did not plan for. The consequence is an outage; the mitigation is detection (a watchdog, a heartbeat, a readback) and an autonomous recovery path. SEFI rates are quoted per device per day and are usually orders of magnitude below the bit upset rate of the same device.

Single event transient (SET)

A voltage pulse appears on an output and then goes away. In digital logic the pulse can be captured by a downstream latch and becomes an upset. In analog and mixed signal parts, operational amplifiers, comparators, voltage references, regulators, converters, the transient can be tens of microseconds long and as large as the supply rail, and what it does depends on the load: a brown out reset from a regulator, a bad sample from a reference, a false trip from a comparator. Transients are the effect that is most specific to the application, which is why the analog transient guideline is organised by device family and by what the load can tolerate. Mitigation is filtering, hold off, redundancy and choosing where in the circuit a transient can do least harm.

3. Destructive effects

Single event latchup (SEL)

The particle turns on a parasitic bipolar structure between the wells and substrate of a bulk CMOS device. Once on, it stays on: the supply current jumps to a high, self sustained level and the only way out is to remove power. If the current is not limited, the part is destroyed by heating within milliseconds; if it is limited and power is cycled quickly, most parts survive, and some survive many cycles. SEL is the effect that dominates commercial part risk assessment because it is common in bulk CMOS, it is worst at high supply voltage and high temperature, and it ends a mission if unprotected. Silicon on insulator and epitaxial processes are much less susceptible. Mitigation is current limiting with autonomous power cycling, proven by a heavy ion test with the protection in place, or a part that has been shown immune to a high LET. The SEL threshold predictor and the SEL test LET tool deal with how much evidence is enough.

Single event burnout (SEB)

In a power MOSFET, a heavy ion track through the drain region turns on the parasitic bipolar transistor under the source, the device goes into avalanche and the localised current melts the structure. It happens only when the drain to source voltage is high enough, which is why derating the operating voltage below the rated voltage is the universal mitigation. The safe voltage depends on the technology and on LET; the derating advisor gives it from measured data rather than the traditional flat 50 or 75 percent rule.

Single event gate rupture (SEGR)

The ion track through the gate oxide of a power MOSFET, together with the field from the applied gate and drain voltages, ruptures the oxide. The gate leaks or shorts permanently. Like burnout it depends on bias, on LET and, unusually, on the ion's energy and range, which makes test design matter. It is mitigated by the same derating, applied to gate voltage as well as drain voltage, and it is the reason power MOSFET tests are specified with particular attention to ion energy.

Single event dielectric rupture (SEDR) and hard errors

A heavy ion ruptures a thin dielectric in an antifuse FPGA, a capacitor or a high field oxide. Related permanent effects include the stuck bit, a memory cell that no longer holds one state because a single ion deposited enough charge in its oxide to shift its threshold permanently. These are rare, they accumulate over the mission, and they consume error correction capacity a bit at a time.

4. Protons cause single event effects too

A proton's own LET is too low to upset most modern parts directly, although the most sensitive devices now upset from direct proton ionization. The main route is a nuclear reaction: the proton strikes a silicon nucleus and the recoil fragments have LET up to about 15 MeV cm2/mg. So a part with a threshold below 15 will upset from trapped protons in the South Atlantic Anomaly and from solar protons, at a rate set by a proton cross section that is measured separately, usually with a 200 MeV beam. Parts with thresholds above 15 are immune to protons and sensitive only to heavy ions. This is also the limit of what a proton test can prove about heavy ion behaviour; the proton proxy tool quantifies the residual risk.

5. How rates are obtained, briefly

Measure the cross section at several LETs with a heavy ion beam, fit a Weibull, take the integral flux of the environment above each LET, and integrate the product with a correction for the angle at which particles cross the thin sensitive volume. The result is events per device per day for the mean environment; repeat it for a solar particle event to get the worst day. For destructive effects the rate is converted into a probability of at least one event over the mission, because a destroyed part does not have a rate. The rate guide walks through the arithmetic with a worked example.

6. Summary table

Frequently asked questions

Related tools and pages

• SEE cross section fitting tool and SEE rate tool.
• SEL threshold predictor, SEL test LET tool, proton proxy tool.
• Analog transient guideline, EDAC tool, power derating advisor.
• SEECA workbench for turning effects into function level requirements.
• Glossary.

References