Power Device Derating Advisor

1. What This Tool Does

Power devices do not fail from heavy ions the way a logic part does. A single ion can turn on the parasitic bipolar structure inside a vertical MOSFET or a rectifier and the device sustains its own destructive current, which is single-event burnout; or the ion track can let the gate dielectric see a field it cannot hold, which is single-event gate rupture. Both are destructive, both are one-shot, and both depend strongly on the applied voltage. The standard mitigation is not a hardened part but a derating: run the device far enough below its rating that an ion cannot start the process.

This tool answers how far. Give it a technology class, a voltage rating, the LET your mission requires immunity to, and the risk you will accept, and it returns a maximum operating voltage with the data behind it.

2. Using It

• Technology class. Structure matters more than material alone, so silicon MOSFETs are split by gate structure (trench, planar VDMOS, superjunction, lateral) rather than lumped, GaN is split into plain enhancement-mode HEMTs and cascode parts, and rectifiers are separate from transistors. Pick the closest match; the tool shows how many test conditions and how much of the LET range sit behind each class.
• Voltage rating. The manufacturer maximum: V_DS for a transistor, V_RRM for a rectifier, or the maximum input voltage for an integrated power part. The model works in the fraction of the rating, which is what lets a 20 V trench MOSFET and a 1200 V SiC MOSFET inform the same fit.
• Required LET immunity. The worst-case LET your mission requires. 37 MeV·cm²/mg is the usual heavy-ion screening requirement; 60 to 75 is used for high-reliability programmes. Above LET 60 the model is held flat, because published threshold curves saturate and the corpus cannot resolve the knee.
• Accepted risk. The probability that a randomly drawn part of that class is adverse at your operating voltage. 10 percent is the default recommendation, 5 percent is conservative, and 50 percent is the median part and is not a design point. This is a per-part probability, not a mission rate.
• What counts as adverse. Burnout and gate rupture only, or also a reported leakage or degradation onset. This is a system question, not a device question: a converter that tolerates a few microamps of extra leakage for the rest of the mission can use the first, a precision path or a part whose leakage runs away with temperature should use the second. The gap is largest for silicon carbide.
• Data included. The vendor screen is a large single-LET dataset of commodity silicon MOSFETs whose method has not been independently verified. It is included by default and can be switched off. Where the two answers differ materially the tool says so; the conservative course is the lower of the two.

3. Reading the answer

The headline is a maximum operating voltage. Below it are the median part (half the class fails below that voltage, so it is not a design point), the class spread, the answer under the other adverse definition, the answer with the vendor screen switched, and a comparison against the flat 50 and 75 percent rules showing the risk each rule actually carries for your class and LET.

Four guards apply. The recommendation is never above the manufacturer rating, since the electrical rating governs; when the risk quantile lands above the rating the tool says no heavy-ion derating is indicated. LET requests above 60 are held at 60 and flagged. A class whose fitted spread sits at the model bound is flagged, because its tail is then set by the bound rather than by data. A recommendation below 5 percent of rating is flagged as effectively unusable, because at that point the honest answer is a qualified part, a different technology, or protection that survives the event.

4. What the numbers say

At LET 37, 10 percent risk, burnout and rupture only: silicon trench 24% of rating (20% with the vendor screen added), silicon planar VDMOS 9%, silicon superjunction 42%, SiC MOSFET 4%, commercial GaN 20%, space-grade GaN 26%, silicon Schottky rectifier 66%, silicon PN rectifier 71%, SiC Schottky rectifier 15%.

The pattern is worth absorbing. The flat 50 percent rule is badly optimistic for commodity trench silicon and for silicon carbide, where the median part is already adverse at half its rating, and unnecessarily harsh for silicon rectifiers, which tolerate far more. A rule that does not know the technology cannot be right for both.

5. How LET is handled

Parts are tested at whatever LET was available, so combining them requires a model of the LET dependence. Pooling every condition and regressing on LET gives a slope indistinguishable from zero, not because LET is harmless but because LET varies mostly between parts and the part-to-part spread is several times larger. The slope is therefore measured within parts, using only devices tested at more than one LET at the same gate bias, which differences out the part term. That gives b = 0.1625 with a 90 percent interval of [0.11, 0.215] from 136 pairs: the tolerable voltage falls by a factor 0.894 per doubling of LET. The effect is real but modest next to the class differences.

6. Caveats

• Ion energy and range are not yet covariates. Burnout and rupture depend on how deep the charge track runs, not only on surface LET, and the corpus contains cases where the same LET at different beam energies gave different thresholds. A recommendation resting on low-energy beam data may be optimistic for the deep tracks of a real cosmic-ray environment.
• Gate bias is recorded but not fitted. Rupture thresholds move strongly with off-state gate voltage; the model averages over the biases that were tested, so a part run at a strongly negative gate bias sits at the pessimistic end of that average.
• Within-class spread is wide, and in several classes the data do not resolve it. Two parts with the same rating from the same vendor in the same package can differ by an order of magnitude in burnout voltage. That is why the recommendation sits in the lower tail rather than at the median.
• SiC JFET, GaN cascode and IGBT have too few conditions to fit, and the SiC and GaN classes rest on small samples whose intercepts are pulled toward the population.
• This is a population prior for a part you have not tested. It does not know your lot, your bias conditions, your thermal design or your protection circuit, and it is not a substitute for qualifying a part you intend to fly.

7. References