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Latchup or High-Current SEFI?

The supply current jumps during a heavy ion run. Whether it was latchup or a functional interrupt decides the protection design, the rate and the test plan, and three bench tests usually settle it

During a heavy ion run the supply current steps up and stays up. The log says SEL, the part is power cycled, and the event goes into the latchup cross section. Sometimes that is right. Sometimes the ion flipped a bit in control logic, the logic parked two drivers against each other or left a charge pump running, and what drew the current was a functional interrupt. The two are different physics. Latchup is a parasitic thyristor held on by the supply; it collects charge from deep in the substrate and it gets much easier as the part heats up. A high-current SEFI is a logic state, set by an upset a micrometer or two below the surface, and it barely notices either depth or temperature. Mixing them up misclassifies a destructive failure mode in both directions.

Fire an ion in each mode, change the LET, range, temperature and supply, then try the reset, the supply step-down and the power cycle. The hidden mode picks one of the model's paths at random and hides the silicon, so you can practice reading the tests from the supply current alone. The silicon pane opens as a rotatable block cut at the strike (drag it, or switch to the flat section); its front face is the section, its top face the layout the ion sees. The angle slider tilts the track and applies the cosine law (effective LET of LET divided by cos θ, depth reached of range times cos θ), the geometric rule behind the tilted-beam method of [2]. That rule is a first approximation only: in 65 nm SRAMs the latchup cross section at grazing incidence generally depended on the direction of the tilt relative to the n-well, a lateral effect that simulation predicted [9] and the same group then measured [17]. The model shows the mechanisms and the variables that move them; it cannot tell you what a given part did. The numbers are illustrative; the measurements behind each effect are below.

Same symptom, two mechanisms

Both show up as a step in supply current that outlasts the ion. What holds the current, and where the ion had to deposit its charge to start it, are different, and every test below exploits one of those differences.

Latchup (SEL)High-current SEFI
Where the charge that matters is collectedThe well and the substrate beneath it. Sensitive volumes fitted for 1990s parts start 2 to 5.5 µm down and are 6 to 22 µm thick [2].A control latch, configuration cell or state register, a micrometer or two down.
What keeps the current flowingA parasitic PNPN thyristor, held on by the supply as long as it stays above the holding voltage.A logic state: two drivers in contention, a mode or pump left on, a configuration engine writing the wrong frames [13].
What clears itRemoving the supply, or pulling it below the holding voltage.A reset, reconfiguration or scrubber halt with power on, unless the upset hung the control interface.
Supply stepped below the holding voltageCurrent falls to normal.Current stays up, lower in proportion to the supply.
Current levelSet by the thyristor and the series resistance: often hundreds of milliamps to amps, or a small micro-latch step.Set by the circuit: often a repeatable step, sometimes a creep tied to an operation such as scrubbing [13].
TemperatureOnset LET falls about 2.5 times and the saturated cross section rises 2 to 3 times between room temperature and 125 °C [6].Usually weak [14], with exceptions in hardened cells [8].
Ion rangeA short-range ion under-tests it: the cross section fell about 100 times when the range dropped from 18 to 11.5 µm at the same LET [1].Barely matters once the ion reaches the surface circuitry.
Can it destroy the partYes: heating and metal damage while latched [16].Usually not, but contention currents above an ampere heat the die [13].

The three bench tests, and how each can mislead

1. Reset with power on

If a reset, a reconfiguration or halting the scrubber brings the current back while the supply stays on, it was not latchup: a thyristor does not care what the logic is told. Pechenkin and co-workers adopted this as their rule on a Kintex-7 after finding that functional interrupt currents built up slowly and tripped a fixed latchup threshold [12]. Lee, Swift and Wirthlin traced the high-current events on Xilinx 7-series and UltraScale parts to an upset in the configuration engine that wrote frames to the wrong address; the contention current climbed at a rate set by the scrub rate, passed 10 A in one case, and cleared with the PROG reset unless the supply's over-current protection had browned the part out first [13]. The test misleads in one direction: a SEFI that hangs the control interface ignores the reset, which is how functional interrupts end up in databases as latchup [14].

2. Step the supply below the holding voltage

A thyristor needs its holding voltage and a logic state does not. Lower the supply in small steps, below the latchup holding voltage but above the level where the logic resets itself. Latchup goes out and the current falls to normal; a SEFI's current stays up, lower in proportion to the supply. Pieper and co-workers stepped the supply of a 7 nm FinFET part down 10 mV at a time and watched micro-latches drop out one by one; raising it again restarted them with no source present, and the part kept working throughout [11]. It misleads in two ways: a step below the logic's reset level clears a SEFI too and makes it look like latchup, and near the holding voltage a latch can restart when the supply comes back.

3. Power cycle

It clears both, so on its own it says nothing about which one it was [14]. It is the recovery, not the diagnosis. Afterwards check function and the supply current against the pre-run values: Vorobiev and co-workers held voltage supervisors in latchup for five minutes at a 2 A limit, and one of the three parts of one type failed [16].

Two more observations help when the tests disagree. The shape of the current: stable, discrete steps point to a latch, while a creep that follows an operation points to logic [13, 15]. And where it happens: a pulsed laser or an infrared camera can find the latched site [12]. High-current events come in more than two kinds. Mauguet and co-workers read discrete, stair-step currents on an MRAM that only a power cycle cleared as localized latchup [15], and a SEFI followed by a power cycle can draw an inrush that trips the latchup detector again [15].

Supply current steps up and stays uprecord the rail, the level and the operation1. Reset or reconfigure, power stays onhalt the scrubber if one is runningHigh-current SEFIcurrent back to normal:a logic state held itclearednot cleared2. Step VDD below the latchup holding voltagebut above the level where the logic resets(find the holding voltage in 10 mV steps if unknown)current falls to normalLatchuponly a thyristor needs aholding voltage to stay onstays up, lower with VDDHigh-current SEFI, interface hunga reset never arrived; driversor a pump are held on3. Power cycle, then check function and supply current against the pre-run valuesA power cycle clears both, so on its own it does not tell them apart. Confirm with the beam: latchup onset falls withtemperature and needs range to the full sensitive depth; a SEFI barely notices either (see below).

The sequence in the order that preserves the most information. Record the current after every step.

Why temperature separates them

In a latchup path the collected charge has to push the well and substrate potentials far enough to turn on a parasitic junction. Heat raises the well and substrate resistance (about twice as high at 125 °C) and lowers the junction turn-on voltage (to about 0.7 of its room temperature value), so the same charge goes further. Johnston and co-workers measured onset LETs about 2.5 times lower at 125 °C, with saturated cross sections 2 to 3 times higher [6]. On a 12 µm epitaxial SRAM the threshold fell by about half between 25 and 100 °C [7], and Kolasinski and co-workers concluded that "for many if not most devices, room temperature represents a threshold region for latchup" [8]. Holding voltage and holding current fall with temperature as well [9], so a hot part latches more easily and stays latched at a lower supply. On orbit the effect compounds: in one study's model, geostationary rates for five parts rose 5 to 43 times between 25 and 125 °C, partly by extrapolation beyond the temperatures tested [10].

A high-current SEFI starts as an upset in a latch, and upsets usually change much less with temperature. Guillermin and co-workers found high-current events in flash memory about equally likely at 25 and 85 °C and read that as a sign of a non-latchup mechanism [14]. The caveat is real: a resistor-hardened SRAM's upset cross section rose by orders of magnitude with heat [8], so a weak temperature dependence supports a SEFI diagnosis without proving it. The practical rule is the familiar one: test latchup at the highest temperature and supply the part will see, because a room temperature pass is not a flight pass.

Why range separates them

A latchup path collects from the well and the substrate beneath it, so an ion that stops short of the bottom of that volume under-tests it, whatever LET it arrives with. Levinson and co-workers held the LET of iron ions near 30 and shortened their range in silicon from 18.3 to 11.5 µm; the latchup cross section fell by roughly two orders of magnitude [1]. Ecoffet and Duzellier fitted sensitive volumes in five parts that began 2 to 5.5 µm down and were 6 to 22 µm thick [2], and a laser measurement on a 2011 SRAM put a lower bound of 3 µm on the depth, growing with the supply voltage [3]. A control latch sits a micrometer or two down, so once an ion reaches the circuitry its range hardly matters to a SEFI.

Four beams labeled LET 40 at the surfaceLET in silicon against depth, from the SRIM-derived tables in the beam calculator; overlayers and air ignoredlatchup volumes fitted for 1990s parts:about 2 to 25 µm deepcontrol latch, 1 to 2 µm0102030405060020406080100120140160depth in silicon, µmLET, MeV cm2/mgBr-79 at 1.5 MeV/u (low-energy tandem class): range 20 µm, 5.2 pC deposited in the top 25 µmKr-86 at 4.5 MeV/u (LBNL 4.5 MeV/u cocktail): range 48 µm, 10.4 pC deposited in the top 25 µmAg-109 at 15 MeV/u (TAMU K500): range 148 µm, 10.7 pC deposited in the top 25 µmXe-129 at 24.8 MeV/u (TAMU K500): range 269 µm, 10.4 pC deposited in the top 25 µm

All four beams arrive with an LET of 39 to 40. The bromine beam is already past its Bragg peak at the surface: it stops at 20 µm and deposits about half the charge of the others in the top 25 µm, and nothing below. The 4.5 MeV/u krypton beam reaches 48 µm in vacuum, but metal and passivation layers and any air in the path come off that before the ion reaches the silicon.

Energy matters near threshold for a second reason. Dodd and co-workers found latchup cross sections up to 1000 times higher with beams above 10 MeV/u than with 1 to 8 MeV/u beams near LET 15 on some SRAMs, and attributed part of the difference to secondaries from nuclear reactions [4]. For a latchup screen of a bulk part, ask for the range remaining at the bottom of the sensitive volume, after the overlayers and any air, and keep it well beyond 25 µm; for a backside test add the remaining substrate thickness [5]. Epitaxial wafers shrink the volume: on 5 and 7 µm epi versions of one SRAM no latchup was seen at all [7]. The beam calculator gives the range and LET at depth for any facility cocktail and stack of layers.

What the test plan should record

Why it matters after the test

The latchup protection sizing tool places a trip current between the normal load and the latched current. A high-current SEFI can sit inside that window: it trips the limiter and costs a power cycle, or it gets taken for a micro-latch. The SEL threshold predictor and the other latchup tools rest on historical records, and a SEFI logged as latchup makes latchup thresholds look lower than they are, while a latchup logged as a SEFI hides a destructive mechanism. And the two belong in different places in a mission analysis: a SEFI rate goes into the availability model with its reset and recovery time, latchup into the destructive or power cycle budget of the SEE analysis workbook.

Frequently asked questions

If only a power cycle cleared it, was it latchup?

Not necessarily. A SEFI that hangs the control interface ignores a reset and needs a power cycle too, and so does a supply held at its compliance limit. The supply step-down below the holding voltage is the test that separates them.

Can a functional interrupt really draw amperes?

Yes. On Xilinx 7-series and UltraScale FPGAs, an upset in the configuration engine produced contention currents that passed 10 A on the core rail and cleared with a reset [13].

How far below the holding voltage should the step-down go?

Just below it, in small steps: 10 mV steps were used to find the holding voltages of individual micro-latches [11]. Stay above the supply at which the logic resets itself, or the step clears a SEFI too.

Why does ion range matter for latchup but not for upsets?

Latchup collects charge from the well and the substrate beneath it, fitted at 2 to 25 µm deep in 1990s parts [2], while an upset or a SEFI depends on charge within a micrometer or two of the surface. A short-range ion reaches the second but not all of the first.

Is a weak temperature dependence proof of a SEFI?

No. It is consistent with one, but some upset mechanisms are strongly temperature dependent [8]. Use it alongside the reset and step-down tests, not instead of them.

References

  1. J. Levinson, O. Even, E. Adler, et al., "Single Event Latchup (SEL) in IDT 7187 SRAMs: Dependence on Ion Penetration Depth," Proc. RADECS 93, p. 438, 1994.
  2. R. Ecoffet and S. Duzellier, "Estimation of Latch-up Sensitive Thickness and Critical Energy using Large Inclination Heavy Ion Beams," IEEE Trans. Nucl. Sci. 44(6), p. 2378, 1997.
  3. E. Faraud, V. Pouget, K. Shao, et al., "Investigation on the SEL Sensitive Depth of an SRAM Using Linear and Two-Photon Absorption Laser Testing," IEEE Trans. Nucl. Sci. 58(6), p. 2637, 2011.
  4. P. E. Dodd, J. R. Schwank, M. R. Shaneyfelt, et al., "Impact of Heavy Ion Energy and Nuclear Interactions on Single-Event Upset and Latchup in Integrated Circuits," IEEE Trans. Nucl. Sci. 54(6), p. 2303, 2007.
  5. S. Buchner, N. Kanyogoro, D. McMorrow, et al., "Variable Depth Bragg Peak Method for Single Event Effects Testing," IEEE Trans. Nucl. Sci. 58(6), p. 2976, 2011.
  6. A. H. Johnston, B. W. Hughlock, M. P. Baze and R. E. Plaag, "The Effect of Temperature on Single-Particle Latchup," IEEE Trans. Nucl. Sci. 38(6), p. 1435, 1991.
  7. L. S. Smith, D. K. Nichols, J. R. Coss, et al., "Temperature and Epi Thickness Dependence of the Heavy Ion Induced Latchup Threshold for a CMOS/EPI 16K Static RAM," IEEE Trans. Nucl. Sci. 34(6), p. 1800, 1987.
  8. W. A. Kolasinski, R. Koga, E. Schnauss and J. Duffey, "The Effect of Elevated Temperature on Latchup and Bit Errors in CMOS Devices," IEEE Trans. Nucl. Sci. 33(6), p. 1605, 1986.
  9. J. M. Hutson, J. D. Pellish, G. Boselli, et al., "The Effects of Angle of Incidence and Temperature on Latchup in 65 nm Technology," IEEE Trans. Nucl. Sci. 54(6), p. 2541, 2007.
  10. E. V. Mrozovskaya, P. A. Chubunov, S. Iakovlev and G. I. Zebrev, "Investigation and Simulation of SEL Cross Sections at Different Temperatures," IEEE Trans. Nucl. Sci. 69(7), p. 1587, 2022.
  11. N. J. Pieper, Y. Xiong, A. Feeley, et al., "Micro-Latchup Location and Temperature Characterization in a 7-nm Bulk FinFET Technology," RADECS 2021.
  12. A. A. Pechenkin, A. A. Novikov, M. M. Novikova, et al., "SEL and SEFI Discrimination in Kintex-7 Using Focused Laser Irradiation," RADECS 2018.
  13. D. S. Lee, G. Swift and M. Wirthlin, "An Analysis of High-Current Events Observed on Xilinx 7-Series and UltraScale Field-Programmable Gate Arrays," IEEE Radiation Effects Data Workshop, 2016.
  14. J. Guillermin, B. Vandevelde, N. Chatry, et al., "High Current Event and Single Event Functional Interrupt in Non-Volatile Memories," RADECS 2018.
  15. M. Mauguet, J. Guillermin, B. Vandevelde, et al., "High Current Events Triggered by Heavy Ion Microbeam and Pulsed Laser on a MRAM," RADECS 2020.
  16. S. L. Vorobiev, O. A. Bakhirko, L. R. Bakirov, et al., "Voltage Supervisors Post Heavy Ion Irradiation Behavior After Holding in SEL," RADECS 2019.
  17. J. M. Hutson, J. A. Pellish, A. D. Tipton, et al., "Evidence for Lateral Angle Effect on Single-Event Latchup in 65 nm SRAMs," IEEE Trans. Nucl. Sci. 56(1), p. 208, 2009.

Seen a high-current event that fits neither column, or a test that settled it? Bring it to the forum.

More guides: COTS Parts in Space · Heavy Ion SEE Test Planning · Not Every Error in the Beam Is a Single Event Effect · Radiation Hardness Assurance for Commercial Space · How to Run a Single Event Effects Analysis · How to Calculate a Single Event Effect Rate from Heavy Ion Test Data · Single Event Effects Explained · Total Dose, Displacement Damage and Single Event Effects Compared · Glossary · All guides

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