Latchup Protection Sizing

Preliminary analysis aid. Check the result against your own analysis and, where needed, a test on the intended part. Full disclaimer.

1. What it calculates

For a part that latches up and is to be flown behind a current limiter, a monitored switch or a series resistor: the trip current window between the load and the latch, the series resistor load line analysis (whether a resistor can starve the latch below its holding current within the load's voltage headroom, the suggested E24 value, latched current and power, collapse time with the local capacitor), the energy delivered per event before and after cutoff, the die hotspot and package temperature against time in the latched state, the latched current against the supply bond wire's fusing current, the time for the rail to fall below the holding voltage and the off time margin, downtime per event, the expected number of events and the per device count to be demonstrated over the mission, and a verification test plan with the protection in the loop, exported as Markdown.

2. Inputs

• Normal operation. Rail voltage, nominal and maximum load current (worst case activity and temperature), inrush or transient peak the limiter must pass without tripping, rail capacitance downstream of the switch, and any parallel load resistance that remains when the part is latched.
• Latched state. Lowest and highest latchup current observed in test at the mission's highest temperature and supply, the measured holding voltage, the holding current (lowest current at which the latch stays on, from a supply sweep during a latch), the supply voltage the latch currents were measured at, and whether a micro latchup (a small stable current increase) was seen. Make sure the events were latchup first: a high-current SEFI can sit inside the trip window, and a reset with power on or a supply step below the holding voltage tells them apart (latchup or high-current SEFI guide).
• Series resistor. The part's minimum supply voltage, the capacitance at the part after the resistor, the resistance (blank for the suggestion) and the resistor's power rating.
• Detection. Margins above the load and below the lowest latch current, the trip current you intend to set, the protection type, and the filter and switch times whose sum is the cutoff time from onset.
• Die, package, wires. Hotspot radius (the size of the latched region; 20 to 100 µm typical), board temperature, a package preset that fills thermal resistance and time constant (editable), and the supply bond wire type.
• Recovery. Off time before re-enable, restart time to function, and the retry count before the protection latches off.
• Mission. Latchup rate per device day, number of devices behind this design, mission days.

3. Calculation

• Window. Trip minimum = max(load, inrush) × (1 + margin); trip maximum = lowest latch × (1 − margin); feasible when maximum exceeds minimum. Ratio = lowest latch over maximum load.
• Series resistor. Latch line V = V_h + I R_latch with R_latch = (V_test − V_h)/I_latch,low; R_drop = (V − V_min)/I_max; R_ext = (V − V_h)/I_hold − R_latch; window when R_ext < R_drop; latched current (V − V_h)/(R + R_latch); capacitor transient integrated numerically for collapse time and die energy; recharge 3RC.
• Energy. V × I_latch,high × (filter + switch) plus C(V² − V_h²)/2.
• Hotspot. Disc of radius a on semi infinite silicon: rise = min(2q√(αt/π)/k, P/(πka)) with q = P/(πa²), k = 150 W/m/K, α = 8.8e-5 m²/s; plus a package rise θP(1 − e^−t/τ); plus board temperature. Bands at 150, 250 and 400 C.
• Bond wire. Highest latch current over a typical sustained fusing current for the selected wire.
• Discharge. C(V − V_h)/I_latch,low with the latched part as a constant current sink; RC ln(V/V_h) for the load resistance alone. Off time margin is off time over the constant current figure.
• Mission. Poisson with mean rate × devices × days; per device 99 percent count; test count = max(10, 3 × per device 99 percent count).

4. Assumptions

• The latched part draws a roughly constant current until the rail nears the holding voltage; for the resistor analysis it follows a straight line between the test point and the holding point.
• The heat is released in one disc shaped region at the die surface; the die is thick compared with the region; silicon properties are those at room temperature.
• Package heating is a single time constant; thermal resistance is junction to board.
• Bond wire fusing values are typical sustained figures for short wires; parallel wires share current.
• The protection circuit itself is radiation tolerant and its timing does not change with dose.

5. Implementation notes

• The energy and heating use the highest latch current, the trip window and discharge use the lowest: the damaging event and the escaping event are different events.
• Choosing a package preset overwrites the thermal resistance and time constant fields; edit them afterwards if you have datasheet values.
• The time to 250 C is found on a logarithmic time grid from 1 µs to 1000 s; "never" means the steady state stays below 250 C.
• The plan is plain Markdown built from the inputs; every number in it is a design value to be confirmed by the test.

6. Limitations

• The hotspot radius dominates the temperature result and is rarely known; move it and see. The model gives scaling and order of magnitude, not a design temperature.
• No treatment of multiple supply domains, latch paths that change current level during an event, or the protection circuit's own upset and latchup.
• Silicon conductivity falls with temperature, so the model is optimistic above a few hundred degrees.
• Downtime and mission counts are as good as the rate you enter; use the worst case environment for the survival count.

7. References

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